Platform controller hubs (PCHs) represent a family of successful microchips. I/O functions have been reassigned between a new central hub and the central processing unit (CPU). Certain Northbridge functions, the memory controller, and Peripheral Component Interconnect Express (PCIe) lanes have been integrated into the CPU, while the PCH has taken over the remaining functions. As is the case with most processor environments, their Idle Power should be minimized to meet certain requirements. In many cases, there can be multiple high-speed Serial input/output (I/O) ports (including the universal serial bus (USB)) to accommodate. Hence, it becomes significant to bring down the expenditure for the PCI Express root port Idle Power by several factors.
The FIGURES of the drawings are not necessarily drawn to scale or proportion, as their dimensions, arrangements, and specifications can be varied considerably without departing from the scope of the present disclosure.